1. Field of the Invention
The present invention relates to information processors, and more particularly, to an information processor in which overhead incurred during processing for calling a subroutine and returning therefrom is reduced.
2. Description of the Related Art
In von Neumann type computers, a program counter (hereinafter referred to as PC) indicative of an address of an instruction to be executed is updated to sequentially read and execute programs stored in a memory. In general, central processing units (hereinafter referred to as CPU) of von Neumann type computers need to store, prior to branch from a main program to a subroutine, an address of an instruction to be executed first upon return from a subroutine (hereinafter referred to as a return address).
Description will be given in the following of a conventional information processor including a CPU having a calling instruction for subroutine processing and an instruction to return from the subroutine.
An information processor according to the first prior art is structured to store a return address in a memory by using a general-purpose register as a stack pointer. In this first prior art, a JAL instruction is used as a subroutine calling instruction and a JMP instruction as a returning instruction. JAL instructions are for calling a subroutine by addressing, while JMP instructions are for returning from a subroutine through a register.
Second prior art is disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 63-316134 entitled "Semiconductor Integrated Circuit". This second prior art uses a shift register for subroutine processing in place of a memory used as a stack. In addition, the second prior art uses a CALL instruction as a subroutine processing calling instruction and a RET instruction as a return instruction.
In the following, description will be given of structure and operation of these prior art information processors. The structure of the first prior art is shown in FIG. 5. In the figure, the reference numeral 410 represents an instruction decoder, 440 a PC (program counter), 441 an incrementer which increments the value of the PC440 by "2" or "4" in response to a word change-over signal S34, 501 to 531 general-purpose registers, 500 a general-purpose register whose data is fixed at "0", 600 to 631 two-input AND circuits, 650 a two-input OR circuit, 420 a data bus, and 430 a memory. In the first prior art, the memory 430 is used as a stack for return addresses.
The instruction decoder 410 decodes various kinds of instructions including a subroutine calling instruction and a return instruction and based on the results of the decoding, outputs a read signal (RD signal) S52, a write signal (WR signal) S53, a return signal S54, a save signal S55, register select signals S0 to S31, an address of a subroutine and a word change-over signal S34 indicative of a byte count of a decoded instruction (length of an instruction). In addition, the instruction decoder 410 outputs 32-bit address data onto the data bus 420.
The incrementer 441 at all times receives an output of the PC440 and in response to the word change-over signal S34, outputs to the PC440 a sum of a counter value ("2" or "4") equivalent to the length in bytes of an instruction being decoded and the output of the PC440.
The return signal S54 output from the instruction decoder 410 is supplied to ones of the respective inputs of the AND circuits 600 to 631. The save signal S55 from the instruction decoder 410 is supplied to one input of the OR circuit 650.
The register select signals SO to S31 correspond to the AND circuits 600 to 631, respectively. More specifically, the register select signal S0 corresponds to the AND circuit 600 and the register select signal S31 to the AND circuit 631. The register select signals S0 to S31 are accordingly supplied to the others of the respective inputs of their corresponding AND circuits 600 to 631.
The AND circuits 600 to 630 obtain the AND of the return signal S54 and the register select signals S0 to S30, respectively. The outputs of the AND circuits 600 to 630 are output as select signals for selecting the corresponding general-purpose registers 500 to 530. More specifically when the logical value of the return signal S54 is 11111 and any of the register select signals S0 to S30 attains "1", one of the outputs of the AND circuits 600 to 630 attains "1" to select the corresponding one of the general-purpose registers 500 to 530.
The word change-over signal S34 output from the instruction decoder 410 is a signal which controls the incrementer 441. The word change-over signal S34 takes the logical value "0" when an instruction being decoded is two bytes long and takes the logical value "1" when an instruction being decoded is four bytes long. The incrementer 441 is controlled to add the count value "2" to the PC440 when the logical value of the word change-over signal S34 is "0" and add the count value "4" when the logical value of the word change-over signal S34 is "1".
The AND circuit 631 attains the AND of the return signal S54 and the register select signal S31 and outputs the same to the OR circuit 650. When the return signal S54 is "1" and the register select signal S31 is "1", the output of the OR circuit 650 takes the logical value "1" to select the general-purpose register 531. In addition, when the logical value of the save signal S55 is "1", the output of the OR circuit 650 takes the logical value "1", to select the general-purpose register 531.
The RD signal S52 and the WR signal S53 are supplied to the general-purpose registers 500 to 531. When the RD signal S52 takes the logical value "1", data of a general-purpose register being selected is output onto the data bus 420. When the WR signal S53 takes the logical value "1", data on the data bus 420 is written to a selected general-purpose register.
The instruction decoder 410 outputs an address of a subroutine onto the data bus 420 upon completion of write of a return address to a general-purpose register.
FIG. 6 shows a format of instruction codes to be processed by the information processor illustrated in FIG. 5. For calling a subroutine, a JAL instruction 401a shown in FIG. 6 is executed. Bit numbers 15 to 10 of the JAL instruction 401a represent a field of op codes which direct operation of the JAL instruction 401a. Bit numbers 9 to 0 and 31 to 16 represent a field for setting a displacement value indicative of a branch destination. For returning from a subroutine, a JMP instruction 402a is executed. The JMP instruction 402a is arranged as shown in FIG. 6, in which bit numbers 15 to 10 represent an op code field which directs operation of the JMP instruction. Bit numbers 9 to 5 represent an unused field all set to "0". Bit numbers 4 to 0 represent a field for designating a general-purpose register, which field designates the general-purpose registers 501 to 531 by 5-bit binary numbers. An instruction 400a shows a code arrangement of a register-to-register data transfer instruction (MOV, reg, reg).
With reference to FIGS. 5 and 6, the description will be given of operation for calling a subroutine and for returning therefrom. By decoding the JAL instruction 401a, the instruction decoder 410 outputs the RD signal S52 set to "0", the WR signal S53 set to "1", the return signal S54 set to "0", the save signal S55 set to 11111 and the register select signals S1 to S31 all set to "0" and also outputs the word change-over signal S34 set to "1" because the instruction is four bytes long, and then outputs an address of the subroutine onto the data bus 420.
Here, the JAL instruction 401a is described as follows.
JAL Subroutine Name
Description will be given of processing for executing the JAL instruction 401a to store a return address in the general-purpose register 531. In FIG. 5, when the JAL instruction 401a is decoded by the instruction decoder 410, the save signal S55 and the word change-over signal S34 both attain "1", so that a value which is obtained by incrementing the value of the PC440 by "4" is output as a return address onto the data bus 420. At the same time, the output of the OR circuit 650 attains "1" to select the general-purpose register 531. At this time point, since the WR signal S53 is "1", the return address on the data bus 420 is written to the general-purpose register 531.
On the other hand, since the return signal S54 is "0", all of the AND circuits 600 to 631 output "0". No return address is therefore written to the general-purpose registers 500 to 530.
After the saving of the return address, the instruction decoder 410 outputs an address of a subroutine onto the data bus 420 to set an address of a subroutine called by the PC440, thereby transferring control to the subroutine.
As described in the foregoing, because the general-purpose register 531 is regularly used to save a return address, it is necessary, before returning from a subroutine, to store the contents (return addresses) of the general-purpose register 531 in the memory 430 used as a stack in preparation for a further call to another subroutine as soon as the control transfers to the subroutine. Such stacking of a return address is required because when the JAL instruction 401a is executed to call another subroutine prior to return from a first subroutine, the contents of the general-purpose register 531 are rewritten to lose a return address for the main routine.
For returning from the subroutine, the JMP instruction 402a as a return instruction is executed. 5-bit data of the JMP instruction 402 which designates a general-purpose register is decoded by the instruction decoder 410, so that one of the register select signals S1 to S31 for selecting the designated general-purpose register is output. Moreover, by decoding the JMP instruction 402a, the instruction decoder 410 sets the RD signal S52 to "1", the WR signal S53 to "0", the return signal S54 to "1", the save signal S55 to "0" and one of the register select signals S1 to S31 corresponding to the designated general-purpose register to "1".
The JMP instruction 402a is described as follows.
JMP General-Purpose Register Name!
Process of reading a return address by executing the JMP instruction 402a will be described with reference to FIG. 5. Here, description will be given of a case where a general-purpose register for reading a return address is the general-purpose register 531. In FIG. 5, first under the program of the subroutine, a return address is read from the memory 430 which stores return addresses and stored in the general-purpose register 531. Thereafter, the JMP instruction 402a which designates the general-purpose register 531 is executed. As a result of decoding of the JMP instruction 402a, the instruction decoder 410 outputs the return signal S54 and the register select signal S31 both set to "1", so that the output of the OR circuit 650 attains "1" to select the general-purpose register 531. At the same time, the instruction decoder 410 outputs the RD signal S52 set to "1", so that the value of the general-purpose register 531 is output onto the data bus 420. In addition, the value of the data bus 420 is set to the PC440 as a return address.
In the first prior art shown in FIG. 5, for the processing of return address saving and returning by regularly using the general-purpose register 531, the return address is saved in the general-purpose register 531 at the time of a subroutine call and the value of the general-purpose register is stacked and held in the memory 430 in preparation for a next subroutine call. It is further necessary to read the return address held at the memory 430 onto the general-purpose register 531 at the time of return from the subroutine. Return addresses are therefore transferred so frequently between the general-purpose register 531 and the memory 430 for the return address saving and returning processing that an overhead is incurred.
In this regard, specific description will be given in the following, for example, of a case of double nesting of a subroutine, that is, a case where another subroutine is called without returning from a subroutine to a main routine.
FIG. 7 shows nesting operation of subroutines by the JAL instruction 401a and the manner of saving in and returning to the PC440. FIG. 8 shows return address saving and returning processing and the clock count required for the processing at each step of the nesting operation of the subroutines shown in FIG. 7. Here, the program, which is executed in the direction indicated by the arrow, nests out of a main routine R1 into a subroutine SR1 and further into a subroutine SR2. The stack pointer is implemented not by special hardware but by the general-purpose register 503.
When the JAL instruction 401a is executed at Step 701 in the main routine R1, a return address is saved in the general-purpose register 531 to set an address of the subroutine SR1 to PC440. As soon as the control transfers to the subroutine SR1, at Step 702, the contents of the general-purpose register 531 are stored at an address of the memory 430 indicated by the stack pointer (general-purpose register 503) to increment the stack pointer by "4". From Step 702 on, processing of the subroutine SR1 is executed.
When the JAL instruction is executed at Step 703 in the subroutine SR1, a return address is saved in the general-purpose register 531 to set an address of the subroutine SR2 to the PC440. As soon as the control transfers to the subroutine SR2, at Step 704, the contents of the general-purpose register 531 are stored at an address of the memory 430 indicated by the stack pointer to increment the stack pointer by "4". From Step 704 on, processing of the subroutine SR2 is conducted.
When the processing of the subroutine SR2 is completed, the value of the stack pointer is decremented at Step 705 by "4" to call the contents of the memory 430 at an address indicated by the stack pointer into the general-purpose register 531. At Step 706, execution of the JMP instruction 402a results in setting of a return address to the PC440, whereby the control returns to the subroutine SR1.
Then, processing of the subroutine SR1 follows. When the processing completes, the value of the stack pointer is decremented by "4" to call the contents (return address) at an address indicated by the stack pointer into the general-purpose register 531 at Step 707. At Step 708, the JMP instruction 402a is executed to set a return address to the PC440, whereby the control returns to the main routine R1.
Thus it is necessary to store a return address in a memory (stack) and call a return address from the memory at each time of a subroutine call and return from a subroutine, which causes an overhead. As shown in FIG. 7, when another subroutine is called without returning to a subroutine from the main routine, more overhead is incurred by a subroutine call.
The structure of the second prior art is shown in FIG. 9 in which the value of a program counter is saved in a shift register in order to reduce such an overhead caused by the processing for storing a return address in a memory and for returning as required in the first prior art.
In FIG. 9 which shows the structure of the second prior art, the reference numeral 801 represents a 16-bit address bus, 802 a PC for inputting and outputting 16-bit address data D0 to D15 from/to the address bus 801, 803 an instruction decoder circuit for decoding an instruction code which decodes and outputs specific instruction codes (CALL instruction, RET instruction) onto output signal lines 804 and 805, respectively, according to the time of decoding. 806 represents a bi-directional shift register having a last-in first-out function, in which a plurality of stages of registers 806-1 to 806-n are connected. The bi-directional shift register 806 conducts forward shift and backward shift operation in response to the decode output signals 804 and 805 from the instruction decoder circuit 803. The reference numeral 807 represents a control circuit for controlling input/output of data between the PC802 and the shift register 806.
Operation of the second prior art shown in FIG. 9 will be described. When the CALL instruction is executed at the time of a subroutine call, an address (return address) of an instruction existing subsequent to the above-described CALL instruction in the program is indicated by the PC802. Return address, which is the contents of the PC802, is not saved in the memory. A forward shifting operation of the bi-directional shift register 806 is conducted in response to a timing signal generated by a CALL decode output ("1") of the output signal line 804 of the instruction decoder circuit 803 to save the above-described return address in the bi-directional shift register 806.
Then, when the RET instruction is executed upon completion of the subroutine, backward shifting operation of the bi-directional shift register 806 is conducted in response to a timing signal generated by the RET decode output "1" of the output signal line 805 of the instruction decoder circuit 803, whereby the last return address held in the reverse direction of the bi-directional shift register 806 is output first and returned to the PC802 through the control circuit 807.
In addition, when the CALL instruction is successively executed a plurality of times (in other words, the CALL instruction is executed a plurality of times without execution of the RET instructions), forward shifting operation of the bi-directional shift register 806 is conducted every time the CALL instruction is executed as described above. Then, when the RET instruction is executed after the above-described successive execution of the CALL instructions, the up-to-date data of the return addresses held in the bi-directional shift register is read out onto the PC802 by backward shift of the bi-directional shift register 806. When the same number of the RET instructions as that of the CALL instructions are executed, all the return addresses are taken out of the bi-directional shift register 806.
As described in the foregoing, it is unnecessary to use a memory for the purpose of storing and saving return address data of the PC802. Such an overhead as incurred in the first prior art is therefore eliminated.
In the above-described first prior art, because a specific general-purpose register 531 is regularly used to save a return address, every processing for a subroutine call and every processing for returning from a subroutine require a return address of the general-purpose register 531 to be stored in and returned from a memory. As a result, a return address is so frequently transferred between a general-purpose register and a memory that an overhead is incurred to reduce a processing speed.
In the second prior art structured to save a return address in and return the same to a bi-direction shift register, overhead incurred in saving and returning a return address, which is a shortcoming of the first prior art, is reduced. However, the structure of the second prior art needs provision of another dedicated control hardware including a bi-directional shift register. Large scale CPU and more cost are therefore required.
In addition, weighing speed-up of processing against reduction of circuit scale will find it impossible to adopt such a structure as shown in the above-described second prior art into a single-chip microcomputer and the like which attach great importance to the reduction of circuit scale.